Three-dimensional integrated semiconductor structures have been investigated as an approach for improving the performance of a semiconductor product. Density can be upgraded many fold by stacking chips or wafers on top of each other. Significant speed improvement can also be expected because the interconnecting wires linking the vertically stacked wafers or chips are shortened substantially.
The application of three-dimensional (3D) integration techniques to wafer level bonding of front-end-of-the line (FEOL) devices requires devices or circuits to be aligned and bonded to a companion device wafer and that high aspect ratio (height to width ratio of greater than 3.0) metal interconnecting structures, e.g., interlayer vias, be formed through the bonded interface to connect to the FEOL devices.
As such, the prior art 3D integration techniques are quite complicated involving numerous processing steps. Moreover, in prior art 3D integration, the etching of the interlayer via openings must be compatible with multiple materials to open contacts in the integrated structure.
It is well known in the semiconductor art that structures referred to as “CMP fill” must be included in device fabrication designs in order to guarantee uniform thinning via chemical mechanical polishing (CMP), as well as, to provide interlevel structural support in FEOL and back-end-of-the-line (BEOL) integration schemes. The CMP fill structures are checkerboard array of boxes which fill open areas between semiconductor devices. CMP fill structures typically consist of a material stack that contains different types of materials. For example, a CMP fill structure may consist of combinations of polysilicon (polySi) and metal silicide in the FEOL, and Cu metal in the BEOL.
These CMP fill structures as well as multiple layers of dielectrics and metallurgy such as, for example SOT islands, silicon nitrides, silicides, etc, can impose complicated processing schemes, or even barriers to the formation of interlayer contacts required for 3D integration of FEOL structures.
In view of the above, there is a continued need for a method that can selectively prepare 2D semiconductor devices (or structures) for subsequent 3D integration in which the above-mentioned problems can be avoided. In particular, a method is needed for preparing 2D semiconductor devices for future 3D integration that avoids multiple masks and specialized etching processes.